Skew
Skew is the time delta between the actual and expected arrival time of a clock signal. Skew can be either extrinsic or intrinsic. The latter is internal to the driver (generator circuitry) and defined as the difference in propagation delays between the device outputs. On the other hand, extrinsic skew is the time difference due to unbalanced trace lengths and/or output loading.
Types of Skew
1. Output Skew
Output skew (tsk(o)) is also referred to as pin-to-pin skew, output skew is the difference between propagation delays of any two outputs of the same device at identical transitions (i.e., compares tpd(LH) versus tpd(LH) or tpd(HL) versus tpd(HL) for any two outputs). For example, if the propagation delay of the fastest output (tpd(LHn)) is 2 ns and that of the slowest output (tpdLH1) is 2.165 ns, then the output skew is: tsk(o) = tpd(LHn) − tpd(LH1) =−165ps JEDEC defines output skew as: the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads.
2. Part-to-Part Skew
Part-to-part skew (tsk(pp)) is also known as package skew and device-to-device skew. Part-to-part skew is similar to output skew, except that it applies to two or more identical devices. Part-to-part skew is defined as the magnitude of the difference in propagation delays between any specified outputs of two separate devices operating at identical conditions. The devices must have the same input signal, supply voltage, ambient temperature, package, load, environment, etc.
3. Pulse Skew
Pulse skew (tsk(p)) is the magnitude of the time difference between the high-to-low (tPHL) and the low-to high (tPLH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = tPHL − tPLH . Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew
4. Process Skew
Process skew (tsk(pr)) is the difference in propagation delay times between corresponding outputs on any two like devices when both devices operate under identical conditions. Process skew quantifies skew due to process variation in the manufacturing process (skew caused by lot-to-lot variation). It excludes variations in supply voltage, operating temperature, output loading, input edge rate, input frequency, etc. Conceptually, process skew is output skew over several devices.
Process skew is generally specified and production tested under fixed conditions (e.g., VCC = 3.3 V, TA= 25°C, CL = 25 pF, all inputs switching simultaneously).
5. Bank Skew
Bank skew (tsk(b)) is the output skew between outputs (at same bank), of a single device with a single driving input terminal. The main difference between bank skew and output skew is that the latter is the worst-case delta between outputs in any output bank.
6. Inverting Skew
Inverting skew (tsk(inv)) is the skew between specified outputs of a single logic device with all driving inputs connected together and the outputs switching in opposite directions while driving identical specified loads.
7. Multiple-Frequency Skew
Multiple-frequency skew (tsk(ù)) is the skew between the controlled-edge position of two different output frequencies of a PLL or counting device that has more than one output frequency, when both signals are rising or both signals are falling.
8. PLL Tracking Skew
PLL tracking skew is the phase difference between the input clock and output clock due to the PLL’s inability to instantaneously update the output clock when the period of the input clock changes. Tracking skew normally applies to a PLL with SSC induced input clock [4]. Therefore, tracking skew is the phase offset of a PLL resulting from a time-varying reference input. If the total measured phase offset due to tracking skew is lumped with phase jitter, including input jitter, then it is referred to as the accumulated tracking skew. Note that tracking skew can either lead or lag the reference clock input.
9. Input Skew
Input skew (tsk(i)) is the difference between any two propagation delay times that originates at different inputs and terminates at a single output. Input skew describes the ability of a device to manipulate (stretch, shrink, or chop) a clock signal. This is typically accomplished with a multi input gate wherein one of the inputs acts as a controlling signal to pass the clock through. Input skew describes the ability of the gate to shape the pulse to the same duration regardless of the input used as the controlling input.
10. Limit Skew
Limit skew (tsk(l)) is the difference between the greater of the maximum specified values of tPLH and tPHL, and the lesser of the minimum specified values of tPLH and tPHL. Limit skew is not observed directly on a device; rather it is calculated from the data sheet limits of tPLH and tPHL. Limit skew quantifies how much variation in propagation delay times are induced by operation over the entire ranges of VCC, TA, output load, process variation and any other specified operating conditions
11. Board Skew
Board skew (tsk(pcb)) is introduced into the timing system by unequal trace lengths and unequal loading. It is independent of skew generated by the clock driver