Speed Matters: How Ethernet Went From 3 Mbps to 100 Gbps… and Beyond

Archive for October 23, 2011

Backward Error Correction

Backward Error Correction (BEC) is a type of error correction in which the receiver detects an error and sends a request for retransmission to the sender.

BEC protocols impose less bandwidth overhead than Forward Error Correction (FEC) protocols, but require more time and bandwidth to recover from errors.

Backward Error Correction is a better solution when errors are rare and bandwidth should be optimized.

BEC algorithms include:

  • Parity bits
  • CRC (Cyclic Redundancy Check)
  • LRC (Longitudinal Redundancy Check)

 

List of error-correcting codes

  • AN codes
  • BCH code
  • Constant-weight code
  • Convolutional code
  • Group codes
  • Golay codes, of which the Binary Golay code is of practical interest
  • Goppa code, used in the McEliece cryptosystem
  • Hadamard code
  • Hagelbarger code
  • Hamming code
  • Latin square based code for non-white noise (prevalent for example in broadband over powerlines)
  • Lexicographic code
  • Long code
  • Low-density parity-check code, also known as Gallager code, as the archetype for sparse graph codes
  • LT code, which is a near-optimal rateless erasure correcting code (Fountain code)
  • m of n codes
  • Online code, a near-optimal rateless erasure correcting code
  • Raptor code, a near-optimal rateless erasure correcting code
  • Reed–Solomon error correction
  • Reed–Muller code
  • Repeat-accumulate code
  • Repetition codes, such as Triple modular redundancy
  • Tornado code, a near-optimal erasure correcting code, and the precursor to Fountain codes
  • Turbo code
  • Walsh–Hadamard code

Forward Error Correction

Forward error correction

In telecommunication, information theory, and coding theory, forward error correction (FEC) or channel coding is a technique used for controlling errors in data transmission over unreliable or noisy communication channels. The central idea is the sender encodes their message in a redundant way by using an error-correcting code (ECC). The American mathematician Richard Hamming pioneered this field in the 1940s and invented the first error-correcting code in 1950: the Hamming (7,4) code.

The redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message, and often to correct these errors without retransmission. FEC gives the receiver the ability to correct errors without needing a reverse channel to request retransmission of data, but at the cost of a fixed, higher forward channel bandwidth. FEC is therefore applied in situations where retransmissions are costly or impossible, such as when broadcasting to multiple receivers in multicast. FEC information is usually added to mass storage devices to enable recovery of corrupted data.

FEC processing in a receiver may be applied to a digital bit stream or in the demodulation of a digitally modulated carrier. For the latter, FEC is an integral part of the initial analog-to-digital conversion in the receiver. The Viterbi decoder implements a soft-decision algorithm to demodulate digital data from an analog signal corrupted by noise. Many FEC coders can also generate a bit-error rate (BER) signal which can be used as feedback to fine-tune the analog receiving electronics.

The maximum fractions of errors or of missing bits that can be corrected is determined by the design of the FEC code, so different forward error correcting codes are suitable for different conditions.

How it works

FEC is accomplished by adding redundancy to the transmitted information using a predetermined algorithm. A redundant bit may be a complex function of many original information bits. The original information may or may not appear literally in the encoded output; codes that include the unmodified input in the output are systematic, while those that do not are non-systematic.

This allows an error in any one of the three samples to be corrected by “majority vote” or “democratic voting”. The correcting ability of this FEC is:

  • Up to 1 bit of triplet in error, or
  • up to 2 bits of triplet omitted (cases not shown in table).

Though simple to implement and widely used, this triple modular redundancy is a relatively inefficient FEC. Better FEC codes typically examine the last several dozen, or even the last several hundred, previously received bits to determine how to decode the current small handful of bits (typically in groups of 2 to 8 bits).

Averaging noise to reduce errors

FEC could be said to work by “averaging noise”; since each data bit affects many transmitted symbols, the corruption of some symbols by noise usually allows the original user data to be extracted from the other, uncorrupted received symbols that also depend on the same user data.

  • Because of this “risk-pooling” effect, digital communication systems that use FEC tend to work well above a certain minimum signal-to-noise ratio and not at all below it.
  • This all-or-nothing tendency — the cliff effect — becomes more pronounced as stronger codes are used that more closely approach the theoretical Shannon limit.
  • Interleaving FEC coded data can reduce the all or nothing properties of transmitted FEC codes when the channel errors tend to occur in bursts. However, this method has limits; it is best used on narrowband data.

Most telecommunication systems used a fixed channel code designed to tolerate the expected worst-case bit error rate, and then fail to work at all if the bit error rate is ever worse. However, some systems adapt to the given channel error conditions: hybrid automatic repeat-request uses a fixed FEC method as long as the FEC can handle the error rate, then switches to ARQ when the error rate gets too high; adaptive modulation and coding uses a variety of FEC rates, adding more error-correction bits per packet when there are higher error rates in the channel, or taking them out when they are not needed.

Types of FEC

The two main categories of FEC codes are block codes and convolutional codes.

  • Block codes work on fixed-size blocks (packets) of bits or symbols of predetermined size. Practical block codes can generally be decoded in polynomial time to their block length.
  • Convolutional codes work on bit or symbol streams of arbitrary length. They are most often decoded with the Viterbi algorithm, though other algorithms are sometimes used. Viterbi decoding allows asymptotically optimal decoding efficiency with increasing constraint length of the convolutional code, but at the expense of exponentially increasing complexity. A convolutional code can be turned into a block code, if desired, by “tail-biting”.

There are many types of block codes, but among the classical ones the most notable is Reed-Solomon coding because of its widespread use on the Compact disc, the DVD, and in hard disk drives. Other examples of classical block codes include Golay, BCH, Multidimensional parity, and Hamming codes.

Hamming ECC is commonly used to correct NAND flash memory errors. This provides single-bit error correction and 2-bit error detection. Hamming codes are only suitable for more reliable single level cell (SLC) NAND. Denser multi level cell (MLC) NAND requires stronger multi-bit correcting ECC such as BCH or Reed–Solomon.

Classical block codes are usually implemented using hard-decision algorithms, which means that for every input and output signal a hard decision is made whether it corresponds to a one or a zero bit. In contrast, soft-decision algorithms like the Viterbi decoder process (discretized) analog signals, which allows for much higher error-correction performance than hard-decision decoding.

Nearly all classical block codes apply the algebraic properties of finite fields.

Concatenated FEC codes for improved performance

Classical (algebraic) block codes and convolutional codes are frequently combined in concatenated coding schemes in which a short constraint-length Viterbi-decoded convolutional code does most of the work and a block code (usually Reed-Solomon) with larger symbol size and block length “mops up” any errors made by the convolutional decoder. Single pass decoding with this family of error correction codes can yield very low error rates, but for long range transmission conditions (like deep space) iterative decoding is recommended.

Concatenated codes have been standard practice in satellite and deep space communications since Voyager 2 first used the technique in its 1986 encounter with Uranus. The Galileo craft used iterative concatenated codes to compensate for the very high error rate conditions caused by having a failed antenna.

Low-density parity-check (LDPC)

Low-density parity-check (LDPC) codes are a class of recently re-discovered highly efficient linear block codes. They can provide performance very close to the channel capacity (the theoretical maximum) using an iterated soft-decision decoding approach, at linear time complexity in terms of their block length. Practical implementations can draw heavily from the use of parallelism.

LDPC codes were first introduced by Robert G. Gallager in his PhD thesis in 1960, but due to the computational effort in implementing encoder and decoder and the introduction of Reed–Solomon codes, they were mostly ignored until recently.

LDPC codes are now used in many recent high-speed communication standards, such as DVB-S2 (Digital video broadcasting), WiMAX (IEEE 802.16e standard for microwave communications), High-Speed Wireless LAN (IEEE 802.11n), 10GBase-T Ethernet (802.3an) and G.hn/G.9960 (ITU-T Standard for networking over power lines, phone lines and coaxial cable). Other LDPC codes are standardized for wireless communication standards within 3GPP MBMS.

Turbo codes

Turbo coding is an iterated soft-decoding scheme that combines two or more relatively simple convolutional codes and an interleaver to produce a block code that can perform to within a fraction of a decibel of the Shannon limit. Predating LDPC codes in terms of practical application, they now provide similar performance.

One of the earliest commercial applications of turbo coding was the CDMA2000 1x (TIA IS-2000) digital cellular technology developed by Qualcomm and sold by Verizon Wireless, Sprint, and other carriers. It is also used for the evolution of CDMA2000 1x specifically for Internet access, 1xEV-DO (TIA IS-856). Like 1x, EV-DO was developed by Qualcomm, and is sold by Verizon Wireless, Sprint, and other carriers (Verizon’s marketing name for 1xEV-DO is Broadband Access, Sprint’s consumer and business marketing names for 1xEV-DO are Power Vision and Mobile Broadband, respectively.).

Local decoding and testing of codes

Sometimes it is only necessary to decode single bits of the message, or to check whether a given signal is a codeword, and do so without looking at the entire signal. This can make sense in a streaming setting, where codewords are too large to be classically decoded fast enough and where only a few bits of the message are of interest for now. Also such codes have become an important tool in computational complexity theory, e.g., for the design of probabilistically checkable proofs.

Locally decodable codes are error-correcting codes for which single bits of the message can be probabilistically recovered by only looking at a small (say constant) number of positions of a codeword, even after the codeword has been corrupted at some constant fraction of positions. Locally testable codes are error-correcting codes for which it can be checked probabilistically whether a signal is close to a codeword by only looking at a small number of positions of the signal.

Tests for Copper Cable Certification

Wiremap

The Wiremap test is used to identify physical errors of the installation; proper pin termination at each end, shorts between any two or more wires, continuity to the remote end, split pairs, crossed pairs, reversed pairs, and any other mis-wiring.

Propagation Delay

The Propagation Delay test tests for the time it takes for the signal to be sent from one end and received by the other end.

Delay Skew

The Delay Skew test tests for the difference in propagation delay between the fastest and slowest set of wire pairs. An ideal skew is between 25 and 50 nanoseconds over a 100 meter cable. The lower this skew the better, less than 25 ns is excellent, but 45 to 50 ns is marginal.

Cable Length

The Cable Length test verifies that the cable from the transmitter to receiver does not exceed the maximum recommended distance of 100 meters in a 10BASE-T/100BASE-TX/1000BASE-T network.

Insertion Loss

Insertion loss, also referred to as attenuation, refers to the loss of signal strength at the far end of a line compared to the signal that was introduced into the line. This loss is due to the electrical resistance of the copper cable, the loss of energy through the cable insulation and the impedance caused by the connectors. Insertion loss is usually expressed in decibels dB with a minus sign. Insertion loss increases with distance and frequency. For every 6dB of loss, the original signal will be half the original amplitude.

Decibels vs. Voltage

dB

Voltage Ratio

dB

Voltage Ratio

dB

Voltage Ratio

dB

Voltage Ratio

0 1V -13 .224 -6 .500 -19 .112
-1 .891 -14 .200 -7 .447 -20 .100
-2 .794 -15 .178 -8 .398 -30 .032
-3 .707 -16 .158 -9 .355 -40 .010
-4 .631 -17 .141 -10 .316 -50 .003
-5 .562 -18 .125 -11 .282 -60 .001
-12 .250 -80 .000

Return Loss

Return Loss is the measurement (in dB) of the amount of signal that is reflected back toward the transmitter. The reflection of the signal is caused by the variations of impedance in the connectors and cable and is usually attributed to a poorly terminated wire. The greater the variation in impedance, the greater the return loss reading. If 3 pairs of wire pass by a substantial amount, but the 4 pair barely passes, it usually is an indication of a bad crimp or bad connection at the RJ45 plug. Return loss is usually not significant in the loss of a signal, but rather signal jitter.

Near-End Crosstalk (NEXT)

Near-End Crosstalk (NEXT) is an error condition that describes the occurrence of a signal from one wire pair radiating to and interfering with the signal of another wire pair. It is the difference in amplitude (in dB) between a transmitted signal and the crosstalk received on other cable pairs at the same end of the cabling. Higher NEXT values correspond to better cabling performance. A higher value is desirable as it would indicate that the power transmitted is greater in magnitude than the power induced onto another wire pair given that the NEXT measurement is simply a difference calculation. NEXT must be measured from each pair to each other pair in twisted pair cabling and from each end of the connection. NEXT is measured 30 meters (about 98 feet) from the injector / generator. Lower near end crosstalk values correspond to higher overall circuit performance. High NEXT values on a UTP LAN that will be using an older signaling standard (IEEE 802.3i and earlier) are particularly detrimental. It could be an indication of improper termination.

Power Sum NEXT (PSNEXT)

Power Sum NEXT (PSNEXT) is the sum of NEXT values from 3 wire pairs as they affect the other wire pair. The combined effect of NEXT can be very detrimental to the signal.

The Equal-Level Far-End Crosstalk (ELFEXT)

The Equal-Level Far-End Crosstalk (ELFEXT) test measures Far-End Crosstalk (FEXT). FEXT is very similar to NEXT, but happens at the receiver side of the connection. Due to impedance on the line, crosstalk diminishes the signal as it gets further away from the transmitter. Because of this, FEXT is usually less detrimental to a signal than NEXT, but still important nonetheless.

Power Sum ELFEXT (PSELFEXT)

Power Sum ELFEXT (PSELFEXT) is the sum of FEXT values from 3 wire pairs as they affect the other wire pair.

Attenuation-to-Crosstalk ratio (ACR)

Attenuation-to-Crosstalk ratio (ACR) is the difference between the signal attenuation produced and NEXT and is measured in decibels (dB). The ACR indicates how much stronger the attenuated signal is than the crosstalk at the destination (receiving) end of a communications circuit. The ACR figure must be at least several decibels for proper performance. If the ACR is not large enough, errors will be frequent. In many cases, even a small improvement in ACR can cause a dramatic reduction in the bit error rate. Sometimes it may be necessary to switch from un-shielded twisted pair (UTP) cable to shielded twisted pair (STP) in order to increase the ACR.

Power Sum ACR (PSACR)

Power Sum ACR (PSACR) done in the same way as ACR, but using the PSNEXT value in the calculation rather than NEXT.

DC Loop Resistance

DC Loop Resistance measures the total resistance through one wire pair looped at one end of the connection. This will increase with the length of the cable. DC resistance usually has less effect on a signal than insertion loss, but plays a major role if power over Ethernet is required. Also measured in ohms is the characteristic impedance of the cable, which is independent of the cable length.

Copper Cable Certification

Copper Cable Certification

In copper twisted pair wire networks, copper cable certification is achieved through a thorough series of tests in accordance with Telecommunications Industry Association (TIA) or International Organization for Standardization (ISO) standards. These tests are done using a certification-testing tool, which provide “Pass” or “Fail” information. While certification can be performed by the owner of the network, certification is primarily done by datacom contractors. It is this certification that allows the contractors to warranty their work.

Need for certification

Installers who need to prove to the network owner that the installation has been done correctly and meets TIA or ISO standards need to certify their work. Network owners who want to guarantee that the infrastructure is capable of handling a certain application (e.g. Voice over Internet) will use a tester to certify the network infrastructure. In some cases, these testers are used to pinpoint specific problems. Certification tests are vital if there is a discrepancy between the installer and network owner after an installation has been performed.

The Standards

The performance tests and their procedures have been defined in the ANSI/TIA/EIA-568-B.1 standard and the ISO/IEC 11801 standard. The TIA standard defines performance in categories (Cat 3, Cat 5e, Cat 6) and the ISO defines classes (Class C, D, E, and F). These standards define the procedure to certify that an installation meets performance criteria in a given category or class.

The significance of each category or class is the limit values of which the Pass/Fail and frequency ranges are measured; Cat 3 and Class C (no longer used) test and define communication with 16 MHz bandwidth, Cat 5e and Class D with 100 MHz bandwidth, Cat 6 and Class E up to 250 MHz, and Cat 7 and Class F with a frequency range through 600 MHz.

The standards also define that data from each test result must be collected and stored in either print or electronic format for future inspection.

The Tests

Test Parameter

TIA-568-B

ISO 11801:2002

Wiremap Pass/Fail Pass/Fail
Propagation Delay Pass/Fail Pass/Fail
Delay Skew Pass/Fail Pass/Fail
Cable Length Pass/Fail Information only
Insertion Loss (IL) Pass/Fail Pass/Fail
Return Loss (RL) Pass/Fail (except Cat3) Pass/Fail
Near-End Crosstalk (NEXT) Pass/Fail Pass/Fail
Power Sum NEXT (PSNEXT) Pass/Fail Pass/Fail
Equal-Level Far-End Crosstalk (ELFEXT) Pass/Fail Pass/Fail
Power Sum ELFEXT (PSELFEXT) Pass/Fail Pass/Fail
Attenuation-to-Crosstalk Ratio (ACR) Information only Pass/Fail (except Class C)
Power sum ACR (PSACR) Information only Pass/Fail (except Class C)
DC Loop Resistance Pass/Fail

Phase Offset

Phase Offset (Phase Error)

Phase offset/phase error is the time difference between the reference input clock and the feedback input to the phase detector of a PLL. The two types of phase error, static and dynamic phase errors, are defined below.

Types

1. Static Phase Offset

Static phase offset (t(∅)) is the time difference between the averaged input reference clock and the averaged feedback input signal when the PLL is in locked mode. The word average implies that a comparison is made between the input of the PLL and its feedback over several thousand periods, and the resulting time differences are averaged. This method excludes jitter components, hence the name static phase offset.

2. Dynamic Phase Offset

Dynamic phase offset (td(.)) is the phase difference between input clock and output clock due to the PLLfs inability to instantaneously update the output clock when the period of the input clock changes (due to input-clock SSC). This is also referred to as tracking skew. The dynamic phase offset includes jitter (specification not yet finalized in JEDEC).

Propagation Delay

Propagation Delay

Propagation delay (tpd) is the time between the specified reference points on the input and output voltage waveforms with the output changing from one defined level (high-to-low) to the other (low-to-high) defined level (tpd= tPHL or tPLH).

Types

1. Propagation Delay Time, High-to-Low Level Output

Propagation delay time, high-to-low level output (tPHL) is the time between the specified reference points on the input and output voltage waveforms with the output changing from the defined high level to the defined low level.

2. Propagation Delay Time, Low-to-High Level Output

Propagation delay time, low-to-high level output (tPLH) is the time between the specified reference points on the input and output voltage waveforms with the output changing from the defined low level to the defined high level.

Skew & Its Types

Skew

Skew is the time delta between the actual and expected arrival time of a clock signal. Skew can be either extrinsic or intrinsic. The latter is internal to the driver (generator circuitry) and defined as the difference in propagation delays between the device outputs. On the other hand, extrinsic skew is the time difference due to unbalanced trace lengths and/or output loading.

Types of Skew

1. Output Skew

Output skew (tsk(o)) is also referred to as pin-to-pin skew, output skew is the difference between propagation delays of any two outputs of the same device at identical transitions (i.e., compares tpd(LH) versus tpd(LH) or tpd(HL) versus tpd(HL) for any two outputs). For example, if the propagation delay of the fastest output (tpd(LHn)) is 2 ns and that of the slowest output (tpdLH1) is 2.165 ns, then the output skew is: tsk(o) = tpd(LHn) − tpd(LH1) =−165ps JEDEC defines output skew as: the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads.

2. Part-to-Part Skew

Part-to-part skew (tsk(pp)) is also known as package skew and device-to-device skew. Part-to-part skew is similar to output skew, except that it applies to two or more identical devices. Part-to-part skew is defined as the magnitude of the difference in propagation delays between any specified outputs of two separate devices operating at identical conditions. The devices must have the same input signal, supply voltage, ambient temperature, package, load, environment, etc.

3. Pulse Skew

Pulse skew (tsk(p)) is the magnitude of the time difference between the high-to-low (tPHL) and the low-to high (tPLH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = tPHL − tPLH . Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew

4. Process Skew

Process skew (tsk(pr)) is the difference in propagation delay times between corresponding outputs on any two like devices when both devices operate under identical conditions. Process skew quantifies skew due to process variation in the manufacturing process (skew caused by lot-to-lot variation). It excludes variations in supply voltage, operating temperature, output loading, input edge rate, input frequency, etc. Conceptually, process skew is output skew over several devices.

Process skew is generally specified and production tested under fixed conditions (e.g., VCC = 3.3 V, TA= 25°C, CL = 25 pF, all inputs switching simultaneously).

5. Bank Skew

Bank skew (tsk(b)) is the output skew between outputs (at same bank), of a single device with a single driving input terminal. The main difference between bank skew and output skew is that the latter is the worst-case delta between outputs in any output bank.

6. Inverting Skew

Inverting skew (tsk(inv)) is the skew between specified outputs of a single logic device with all driving inputs connected together and the outputs switching in opposite directions while driving identical specified loads.

7. Multiple-Frequency Skew

Multiple-frequency skew (tsk(ù)) is the skew between the controlled-edge position of two different output frequencies of a PLL or counting device that has more than one output frequency, when both signals are rising or both signals are falling.

8. PLL Tracking Skew

PLL tracking skew is the phase difference between the input clock and output clock due to the PLL’s inability to instantaneously update the output clock when the period of the input clock changes. Tracking skew normally applies to a PLL with SSC induced input clock [4]. Therefore, tracking skew is the phase offset of a PLL resulting from a time-varying reference input. If the total measured phase offset due to tracking skew is lumped with phase jitter, including input jitter, then it is referred to as the accumulated tracking skew. Note that tracking skew can either lead or lag the reference clock input.

9. Input Skew

Input skew (tsk(i)) is the difference between any two propagation delay times that originates at different inputs and terminates at a single output. Input skew describes the ability of a device to manipulate (stretch, shrink, or chop) a clock signal. This is typically accomplished with a multi input gate wherein one of the inputs acts as a controlling signal to pass the clock through. Input skew describes the ability of the gate to shape the pulse to the same duration regardless of the input used as the controlling input.

10. Limit Skew

Limit skew (tsk(l)) is the difference between the greater of the maximum specified values of tPLH and tPHL, and the lesser of the minimum specified values of tPLH and tPHL. Limit skew is not observed directly on a device; rather it is calculated from the data sheet limits of tPLH and tPHL. Limit skew quantifies how much variation in propagation delay times are induced by operation over the entire ranges of VCC, TA, output load, process variation and any other specified operating conditions

11. Board Skew

Board skew (tsk(pcb)) is introduced into the timing system by unequal trace lengths and unequal loading. It is independent of skew generated by the clock driver